Data stored within semiconductor memories are generally capable of producing only very low level output signals. Typically a bit line is precharged to a high level, and then connected to the memory cell. In the case of dynamic random access memories (DRAMs) a storage capacitor discharges onto the bit line and a voltage difference is produced between the bit line and a dummy cell. In the case of static random access memories, a bit line and inverted bit line are precharged to a high state and then connected to a latch-type cell. The SRAM cell will discharge either the bit line or inverted bit line depending on whether the cell logic is high or low. This generates a voltage difference between the bit line (BIT) and inverted bit line (BIT). In any event, the resulting voltage difference generated by the memory cell is a relatively small signal. In order to provide an adequate output signal for the data read from semiconductor memories, the low level outputs of the memory cells must be amplified.
Sense amplifiers are circuits designed to receive and amplify the low level signal that is output by a memory cell. In the prior art, it has been know to use a differential amplifier as a sense amplifier. The differential amplifier input receives the voltage difference from the memory cell and provides an amplified output. However, this solution does have drawbacks in that differential amplifiers have only a limited gain, and require relatively precise biasing conditions for accurate detection of low level signals.
U.S. Pat. No. 5,231,318, entitled DIFFERENTIAL LATCH SENSE AMPLIFIER and issued on Jul. 27, 1993 to the present inventor, discloses a more robust design that includes a pair of differential amplifiers; one composed of p-channel devices and one composed of n-channel devices. The differential amplifier pair has cross coupled common inputs and a common output. The common output is coupled to a latch formed by a pair of cross coupled n-channel devices.
Regardless of the improvements in sense amplifier design, sense amplifiers continue to be driven by the low level output from individual memory cells. Clearly, it would be desirable to provide a circuit which could boost the output signals from memory cells prior to applying them to the sense amplifier.